Forum Discussion
Altera_Forum
Honored Contributor
10 years ago1)It's a development board(DE0-Nano Development and Education Board).
2) In altera_epcq_controller_core.vhd i can see signals below that correspond to the serial ones. epcq_dclk : out std_logic; -- conduit_epcq_dclk epcq_scein : out std_logic_vector(0 downto 0); -- conduit_epcq_scein epcq_sdoin : out std_logic_vector(0 downto 0); epcq_dataout : in std_logic_vector(0 downto 0) := (others => '0'); -- epcq_dataout.conduit_epcq_dataout I still have a doubt how i can configure Dual purpose pins of DCLK,nCEO and ... If there are configured as regular I/O, i can't boot both hardware and software. I had to configure dclk and nceo as programming pin and DATA[0] and nCSO as compiler configured. I didn't find any datasheet about how to do that. I seems to be different with the other version of Quartus, because the serial signals were exported not the case with Quartus 15.0.