boot NIOS and FPGA from EPCS flash

Ok Daixiwen, thank you.

You said in one post that serial flash can't be accessed with IOWR/IORD macros

/* write to flash 32 bits at a time */

IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write);

But, even if I use the alt_write_flash / alt_read_flash functions, the alt_epcq_controller_write_block/ alt_epcq_controller_read functions are called by the first one. And so IOWR/IORD macros.

It's normal ?

Also I would like to explain you a situation that debug mode gives me. The written data is 0x3fe3d70a.

3f e3 d7 0a - written data

0a d7 e3 3f - endian swapped

9f f1 6b 05 - it's like right shifted (when write in the memory) 0x9ff16b05>1 = 3FE2D60A

0x04800000 : 0x4800000 <Hex>

Address 0 - 3 4 - 7 8 - B C - F

04FB0000 056BF19F FFFFFFFF FFFFFFFF FFFFFFFF

04FB0010 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF

04FB0020 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF

the data is being endian swapped first then shifted right between the time it is written and when its read, which means somewhere there are an incorrect number of serial shifts to load all the data being written or read back.

How can I looking at the serial lines with signaltap ? I didn't find them in my entity.

Best regards