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2) The device is closed only when is fails to open. So i don't need to reopen it when i want to write or read.
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It's not the case in the example code you presented here:
printf("passed.\n\r");
printf("Exiting Flash Tests\n\r");
finished:
alt_flash_close_dev(fd);
return ret_code;
}
You write "Exiting Flash Tests" but you still execute alt_flash_close_dev() before returning, even if the test succeeded.
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May be it's a configuration problem.
With my EPCS device i can boot both the FPGA configuration and Nios II software.
I'm using the Quartus 15.0, When i add the EPCS controller, the DATA, DCLK, ASDI, and nCS signals are not exported to Nios
entity.To add the EPCS controller i have two choice,
altera serial flash controller or
legacy epcs/epcqx1 flash controller, i took the first one, it's right ?. In device and pin options, I configured DCLK & nCEO as as as compiler, ASDI & cCS as compiler configured, if not I can't boot from the Flash.
Hope that help to understand my problem.
Best regards
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No, I think your configuration is correct. The fact that your init function displays the correct flash size shows that the driver managed to ask the flash it's ID and got a valid answer. So I think the flash is connected correctly and you are using the correct controller.
Your image is difficult to see (the forum has the nasty habit of resizing down all images, it's in fact better to past text directly instead of attaching an image) but I don't see any obvious pattern such as a problem with the erasing part. I'm sorry I don't have any more ideas to help you right now, except looking directly at the serial lines (either with a scope or with signaltap) to see which commands the controller is sending to the flash. Another and maybe easier alternative would be to edit the flash driver to print out on the terminal all the commands sent to the SPI master.
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