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I do have a testbench for the module, but haven't yet found an easy way to simulate part of an overall qsys project after Quartus synthesis.
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I haven't used the Altera-defined Avalon-ST components and their associated component customization.
Here's what I would do if I felt that the components were doing the wrong thing;
1) Simulate; add an Avalon-MM Master BFM component to the SOPC System, and use that to generate read/write transactions. (The BFM uses SystemVerilog, so Modelsim-ASE has to use verilog for the SOPC system).
2) Capture the hardware waveforms using SignalTap. Compare to (1).
3) Try various component settings and repeat (1) and (2).
If things don't appear to be correct, then delete the Altera component and write my own :)
Cheers,
Dave
Honored Contributor
