Honored Contributor
Honored ContributorHi Dave,
I do have a testbench for the module, but haven't yet found an easy way to simulate part of an overall qsys project after Quartus synthesis. I have isolated the issue to how I create a new component in qsys with my module, so I think I can show what's going on with the attached screenshots. The Avalon-ST data bus port is defined as above: output reg [31:0] st_data qsys1 - This shows all of my input and output ports with their interface definitions qsys2 - The ST source interface - note that I entered 32 "Data bits per symbol" in the parameter box. The data bits are all correctly ordered as [MSB:LSB] qsys3 - I connect the component to an ST sink (the timing adapter) and feed 2 channels into individual FIFOs qsys4 - The timing adapter (and all downstream ST components) need to be defined with 32 "data bits per symbol" and 1 "Data Symbols per Beat." When I program the Nios CPU to read from the FIFOs, the bit ordering is correct. I get signed integers from the ADC and life is good. The problem is when I change "Data bits per symbol" to 8 in the ST interface definition (qsys2.jpg). I then need to redefine all of my downstream ST components to also have 8 "Data Bits per Symbol" and 4 "Data Symbols per Beat." When the system is built in this way, my data bus is no longer read as [31:0], but rather {[7:0],[15:8],[23:16],[31:24]}. There's nothing really "wrong" with defining 32 bits per symbol, but I want to make this consistent with other ST components to have byte-wide symbols. That way I can connect my components together directly without changing data formats.
