Bit or byte swapping in SDRAM?

I'm confident that my bit Verilog module is coded correctly and I'm not swapping bits. I found the problem to be in the Avalon-ST component definition. I had switched the "Data Bits per Symbol" parameter to 8 so I wouldn't need an adapter down the line.

So, my ST data bus is defined as "output reg [31:0] st_data" in the top level module. I assumed incorrectly that since my data bus is 32 bits wide, if I chose bits per symbol to be 8 then it would automatically set symbols per beat to 4 and my byte ordering would remain intact.

What am I doing wrong here?

-Jason