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Is there any reason the Avalon-ST components would be doing the swapping? Is this an issue with the SDRAM controller? Having some trouble debugging, so any help would be appreciated.
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Be careful if you are coding in VHDL if you have code like this;
signal d : std_logic_vector(31 to 0);
signal q : std_logic_vector(0 to 31);
since
q <= d;
will bit-swap. Whereas
process(d)
begin
for i in 0 to 31 loop
q(i) <= d(i);
end loop;
end process;
will retain the same bit index assignments between q and d.
If you have instantiated an IP core with the bus bit order reversed, then you would see this as a bit-reversal in your final design.
Cheers,
Dave
Honored Contributor
