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Altera_Forum
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10 years ago

Best way to share DDR w/ FPGA

I have a rather simple task to perform but I don't know where to start. I'm using a Cyclone V SoCKit board. What I want to do is have the ARM processor write a data table in DDR so that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Murillo: It's up to 4 GB of data that can be updated by the user at any time. Will be 8GB in the final design. This pushes me in to DDR for more space. Output speed is less than 50 megabits per second... so not fast at all compared to DDR storage of the table.

Daixiwen: I think I have the modular SGDMA component installed but my next question is - how do we access this from the CV ARM processor? All of the driver examples I find are written for NIOS.

There is one for CV but how the scatter / gather driver made it in to the kernel is not clear.

I'm using an Atlas / De0-Nano-SoC board.

Regards,

Jon