BeMicro SDK - Nios II/f - Cyclone IV - Performance - dhrystone

The change in the drystone figures when the cache sizes were increased certainly shows that the working set of the test was significantly larger than the cache size in the first test (and possibly still with 8k caches) - so the memory access times dominate.

Changing the memory width to 32bit should reduce the access times. It is also worth checking there are no clock crossing bridges (I doubt running the DDR faster than the nios will gain more than the cost of these bridges).