Basic SDRAM/NIOS question

BadOmen,

You're right, a FIFO is required to ensure that data is always available to be written to the DAC at the right instants. My suggestion is to import the HDL I posted as a streaming Avalon slave, and master that slave with the Avalon DMA. In that system, the DMA's internal FIFO provides the necessary buffering. Depending on various other aspects of your system, it may be necessary to configure the DMA to have a larger FIFO than its default - you'll know you need to do that if the DMA write master isn't able to write to the PIO at the required rates due to an empty FIFO condition (this is easy to observe in ModelSim).

fpgazz, let me know if this suggestion makes sense to you.