Avalon Slave IP with Interrupt Receiver

<div class='quotetop'>QUOTE (MSchmitt @ Jul 24 2009, 04:30 AM) <{post_snapback}> (index.php?act=findpost&pid=23271)</div>

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your hack should be done as follows

assign Sopc_Idle_0_avalon_slave_0_irq = cpu_0_data_master_irq;

instead of

assign Sopc_Idle_0_avalon_slave_0_irq = 0;

Sopc_Idle_0_avalon_slave_0_irq is an input to my module so i do not understand why you create an output in the portlist as this input already exists and the cpu_0_data_master_irq has all informationen needed.

thanks anyway[/b]

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No. You should define the irq signals input of your slave (perhaps called irqs) as an normal conduit input rather than a specialized interrupt receiver. In your top level module (of the project, not your IP&#39;s top level), define a wire like:

"wire [31:0] system_irqs;"

In the instantiation of system_0 in your top level module, add the new port to obtain the irq information:

".system_irq_out(system_irqs),"

and pass it back into your IP by:

".irqs_to_the_Sopc_Idle_0_avalon_slave_0(system_irqs),"

and put some comments in your top-level module to document the manual changes that were necessary to add the port in system_0.v

This way, your IP is still a standard avalon MM IP that gets it&#39;s information the normal way by passing in the irqs info to one of it&#39;s ports from the top level project file.

And I disagree that what I am suggesting is a "hack". If there was an option to expose the irq signals with a check-box in SOPC builder, the code would be generated almost exactly as I describe. Unfortunately, there isn&#39;t. I am 100% positive this is the most direct and correct way to do this. I would call it a necessary "work around" due to SOPC builder not having an option to expose irq signals to the top-level module. That is why I said it might be a feature request for the next version of Quartus II.

P.S. Thanks for all the posts you make to help others. You are quite active!