Forum Discussion
Altera_Forum
Honored Contributor
16 years agoMySupport showed my a solution that doesn't work here due to errors from sopc.
so still waiting for new ideas. they added a master just for dummy purposes but this master needs to feed a slave. Your hack is one way to go as a workaround, and i will go that way if there won't be a easy solution to keep the automatic generation process alive. such a hack can get forgotten and is gone when somebody else runs the generation scripts. your hack should be done as follows assign Sopc_Idle_0_avalon_slave_0_irq = cpu_0_data_master_irq; instead of assign Sopc_Idle_0_avalon_slave_0_irq = 0; Sopc_Idle_0_avalon_slave_0_irq is an input to my module so i do not understand why you create an output in the portlist as this input already exists and the cpu_0_data_master_irq has all informationen needed. thanks anyway