Avalon Slave IP with Interrupt Receiver

Here's a solution. You need to modify the generated SOPC file to add a 32 bit output port in the port list (perhaps called system_irq_out).

Search the file for "module system_0" (or whatever your system is named).

Add:

"system_irq_out,"

in the port list.

Define the port:

"output [31:0] system_irq_out;"

anywhere where the other ports are defined.

Add:

"wire system_irq_out = cpu_0_data_master_irq;"

anywhere after the port list with the other wire declarations.

then you have exposure of these irq signals to your top-level module, which can be passed as a normal 32-bit input signal into your custom IP.

Yes....kind of sucks to have to do this everytime you re-build the system in SOPC builder, but it isn't too much work. Saves a lot of complexity for you. You have to re-adjust your thinking that this is a "hack". It isn't. The SOPC builder's generated verilog output for your system specification is just a verilog file, just like any other, as far as Quartus II's compiler is concerned. And it did 99.9999% of the work for you and did it very well. But, for your case, you need these IRQ signals, and SOPC builder doesn't have a feature that you can check to expose these signals. Perhaps it could be a feature request to be built into the next version of Quartus II.

It beats making another memory master, and slave just to obtain the irq signals. To me, that is a hack, rather than doing it in a straight-forward way.