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Altera_Forum
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11 years ago

Avalon-MM-Slave address alignment

Hi All I have aquestion regarding the address alignment of a an-MM slave. My MM-Save has an avs_readdata and avs_writedata port each 512 bit wide. Now I'm trying to write the custom prip...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It is a long time since I've looked at the options.

ISTR there being one to request the cache do bursts.

But it won't generate bursts longer than a cache line.

An alternate approach is to dual port an M9K block as tightly coupled data memory.

That will give the nios the same access times as a data cache hit.

You need to make sure the m9K block is set for OLD_DATA (which implies single clock mode).