If your master is fairly well self contained you might not need to write much testbench code. If it takes Avalon accesses to your core to start it up I would recommend using a bus functional model to start it up. Based on what you described I would suspect there could be a problem with the logic leading up to the first read. I would be careful since if your master is not following the spec due to a bug you could run into a really tricky corner later down the road that would be hard to debug. The fabric doesn't have much or any logic to 'fix up' the fabric after a master or slave violates the spec and those are some of the trickiest issues to debug from my own experience without simulating the system.