FPGA image upload. Do you mean the bug only happens for the first read or are you downloading Nios II code? If you are downloading code maybe your system is being reset.
Another thing that could be happening.... are you reading from DDR SDRAM by any chance? Those memory controllers perform a calibration cycle after reset and it takes a while (150us I think....) So perhaps your master is reading from that memory and it's just taking a long time due to the controller performing calibration. The easiest way to find this out would be to remove any watchdog type features and make your hardware perform a single read. If the calibration is holding things up then your read will return around 150us later.