Avalon-MM Master reading

The problem solved and the system works fine.

I've made separate writing and reading masters. Writing master writes using simple write (write assert on data valid and provide data+address). Reading master use bursts. However I had to add watchdog counter for data loss somewhere in the session beginning:

I wait for readdatavalid to go high, then count the packets, but somehow, the first read signal assert doesn't return me data in some time I have to reassert read signal again. This only occurs somewhere after fpga image upload and never in the future.