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Altera_Forum
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15 years ago

Avalon-MM master and cache

Hi, I have designed a fifo controller for a sopc system based on Nios II -f with data cache. It is used to read data from FIFO to SRAM and consists of a avalon-MM slave interface and a master inte...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

In this case the addresses you are accessing uncached are presumably an avalon slave.

The important thing there is to ensure that you NEVER access those addresses with cache enabled accesses.