Avalon MM cycle times for Nios master

I have been making some timing measurements for the Nios Data master port (/f without data cache, Cyclone III at a pedestrian 25MHz) and was wondering if my results match those other people have measured.

My code and all other data is in tightly coupled memory, so the MM switch fabric is largely idle.

My first surprise is that writes are not 'posted' by the data master port, so the Nios cpu stalls for the duration of the Avalon MM cycle.

I also had an expectation (from reading the processor reference) that reads would only stall when the value being read was required (ie be a D-stage stall, not an A-stage stall). This isn't true either, the Nios cpu stalls for the Avalon MM cycle and the result isn't available for a further 2 instructions.

Accesses to a simple PIO peripheral are 3 clocks (read and write).

SDRAM reads 12 clocks.

SDRAM writes, first two writes are 3 clocks (I presume they are buffered for write combining etc), latter ones 8 clocks.

The SDRAM transfers are to addresses that differ enough to require RAS and CAS transfers.

My SDRAM doesn't actually work! (probably clock skew issues) but that probably doesn't matter here.

The above are best case/most frequent clock counts. A moderate fraction of transfers take 1-3 clocks longer. This may be due to contention on the PIO area that contains the counter I'm using, or might be due to the SDRAM using clk/4 or clk/2 for some action.

The other instructions I've tried match the expected values.

Of course, my overall counts are out because the dynamic branch prediction is a mandatory part of the /f Nios cpu - which is no good when you are trying to optimise 500 instructions for worst-case timing.