Avalon CAN controller IP from Opencores

If you look at the timing diagrams for wishbone and Avalon, you will find that they are very close. You should be able to modify the wishbone version to work with Avalon.

I haven't seen any tutorials on this, but it would make a nice project to learn HDL coding. I'd start with simulation. Here is a forum post with more info http://opencores.org/forum,cores,0,863

Followin thuis post http://www.alteraforum.com/forum/showthread.php?t=39783 there is a wrapper already been made for this purposse. Ive compiled the files and works fine. The problem that I have is to attach the signals in qsys when I create a new component. So a first question is in which interface should CAN interface signals attached?

// CAN interface
	input					CAN_clk,
	input					CAN_reset,
	input					CAN_rx,
	output				CAN_tx,
	output       			        CAN_bus_off,
	output       			        CAN_irq,
	output       			        CAN_clkout

Use a conduit. Then you can export the conduit interface in your QSys system to connect those signals to ports on the QSys generated component.