Avalon Bridges

Wow - thanks for your excellent advices - I almost have a solution now!

A short resume of what I did:

1) The critical path was inside the Avalon switch fabric and related to the burst circuitry. Took down the burstwidth from 9 to 6 bits (max burst from 512 to 64) - we only need 48. This chopped the slack from -9 to -5 ns.

2) As a test case I took down the masters from 5 to 1. The slack went down to -1.8 ns - still not good enough. The critical path was now from the burst circuitry to the DDR2 controller.

3) Added one of your registered bridges between the master slave pair - and voila - achieved a slack of 0.5 ns plus reduction of 200 LE's!

4) Added back a master (from 1 to 2) and the slack was back at -3.8 ns. Critical path is now from the avalon_to_avalon_bridgest_0_avalon_slave_arbitrator to burst_0. Don't know what to do to fix this one.

So it is clear that the Altera Megacor DDR2/Avalon/burst combination in a CycloneII -8 is struggling to achieve 125 MHz in general - and in particular with multi master systems. We will thus try to do the 4:1 arbitration for the high speed masters ourselves.

Some further questions:

- What does the current registered bridge do to the burstcont/how should it be set up?

- Are there any conditions/terms to use your bridges in a commercial product?

Looking forward to the new burst supporting version!

Many Thanks & Regards,

Ove Brynestad