Avalon Bridges

I've run into a couple of problems using the bridges. In all cases, I'm using the Asynchronous FIFO'ed bridges.

1) The lpm fifo component declarations include an lpm_width parameter, but this parameter isn't used when declaring the width of the components ports. This causes one of the fifos to error out in compilation due to mismatched port & signal widths. The simple fix is to modify the generated VHDL and use the lpm_width parameter when declaring the components data port widths (as opposed to hard-coding them). I'm not sure how to edit the generator script to correct this.

2) When trying to pass interrupts through the asynchronous FIFO'ed bridge, I get an error when trying to generate if the clock domain on the slave side of the FIFO is pipelined. The error is:

ERROR:

adapter_downstream_pipeline_3/upstream, no device_base (Base_Address = )

255

Haven't figured out how to fix this one.

3) Still not sure what's going on with the .zip within the .zip. Should they be unzipped at the same level or are they hierarchical? The outer .zip file has a directory name embedded, but the inner one doesn't. Where should the inner .zip file be unzipped to (directory name and relative location)?

Any help would be appreciated.