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Altera_Forum
Honored Contributor
13 years agoCreating what you want is as simple as the attached - a VHDL 'interface' that contains the mapping from Avalon signals to RAM signals. Use the component generator to build a _hw.tcl and export the ram_xx signals as a conduit. You can then instantiate the RAM and the control logic on the other port of the RAM outside the SOPC/Qsys system.
Cheers, Dave