Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Auto-Negotiation FAILED

I have a custom board with the 88E111 Ethernet PHY. At one point, the board would light up LEDs indicating a link has been made and it was in 100 mode. I did not change my design at all, but no...
APaga1's avatar
APaga1
Icon for New Contributor rankNew Contributor
6 years ago

--- Quote Start ---

I seem to have fixed the problem, hopefully permanently, by adding a 100 clock cycle delay til I drive the ethernet PHY reset line high when the board powers up.

--- Quote End ---

I am facing the same issue. Can you elaborate where should we add 100 clock cycle delay?

christnp's avatar
christnp
Icon for New Contributor rankNew Contributor
5 years ago

Any luck resolving this?

I had this working on DE2-115 board with the SSS example using Quartus 17.0 and SGDMA; however, upgrading to Quartus 17.1 and now NIOS II SBT BSP requires the mSGDMA module. So I've migrated to mSGDMA... everything builds and runs just fine, but now auto-negotiaton fails.