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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Auto-Negotiation FAILED

I have a custom board with the 88E111 Ethernet PHY. At one point, the board would light up LEDs indicating a link has been made and it was in 100 mode. I did not change my design at all, but no...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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I seem to have fixed the problem, hopefully permanently, by adding a 100 clock cycle delay til I drive the ethernet PHY reset line high when the board powers up.

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I am facing exactly the same error. Could you tell me steps that how you added 100 clock cycle delay to resolve this issue. I am using Quartus 15.1 and Altera DE2-115 board.