Honored Contributor
Honored Contributor1) Assuming you know which pins on your FPGA connect to the TLV320 device, you use the Assignment Editor: http://www.altera.com/literature/hb/qts/qts_qii52013.pdf (http://www.altera.com/literature/hb/qts/qts_qii52013.pdf). If you don't know what pins to assign I would take a look at the documentation/schematics for that board to find out which FPGA pins need assigning.
Assignment Editor will add your pin mapping to the <project>.qsf file in your project folder. You can jump directly to this assignment as well if you right click the pin in the schematic and select locate in the assignment editor (sorry I don't have Quartus II installed on this machine to check the exact name). 2) SPI is made up of four signals: MISO - Master In Slave Out (Rx from the master's point of view) MOSI - Master Out Slave In (Tx from the master's point of view) SCLK - Serial clock SS_N - Slave Select (in this case active low) So a SPI master component will drive out MOSI, SCLK, and SS_N. The SPI master component will take in MISO. I'm not familar with the chip you are using but your wiring sounds right to me. Also as a side note make sure to check the audio codec data sheet since you will need to make sure you meet the timing specification for the device. SPI has two phase and two polarity options so there are 4 combinations (see the SPI documentation to learn more). Some SPI devices also need a delay between the assertion of slave select and when the serial clock starts (in the SOPC Builder component this is called "specific delay"). Last but not least you need to pick a serial clock and data width that matches what the component expects. I hope that helps.
