Assign ports to IO pins in Nios Stratix Board.?

hi,

i've seen many of your post regarding the Stratix device and would like to get your assistance on something I'm working on. I developing a hardware that involves 2 Stratix FPGA devices; one being a FSM controller (1st device) producing control signals and the other device being a computation datapath (2nd device) that functions according to the Controller's signals. All output produced by the Computation Datapath Stratix device is sent back to the Controller Stratix device. Therefore, there is a need for output from the 1st device to be sent as input for the 2nd device, and output from the 2nd device being sent as input to the 1st device.

For this purpose, I assigned the input and output ports of each device to the Proto 1 connector and used the LVTTL IO Standard. However, the problem is when I analyze the output control signals of the 1st device (Controller), it shows errorneous signals being outputted. I'm 100% sure that the design is okay because when both designs (Controller & Datapath) were implemented in one single Stratix device, they worked perfectly. Only when they are separated on two devices, the communication breaks down due to error in outputted signals from IO pins.

Could this be due to the wrong IO Standard being used. What is the proper way to output VHDL design ports to the Stratix deice IO pins? Can the Proto1 IO pins be used to output signals to external devices? Are there any settings such as VRef or VCCO that need to be configured. I read in one of your post that one has to be careful of which IO bank is selected for IO pins to external devices.

Please help...it is of great urgency and importance to me.

Thanks.