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The problem arises when we then try to update the flash via the NIOS (using EPCS flash controller) it does not work because the Nios cannot open the device. It looks like the AS controller still has control of the SPI pins, presumably because the configuration stream has not technically finished (it contains an image for another FPGA which is not present).
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I don't think the AS controller ever prevents Nios from accessing the flash via the EPCS controller. The SOF file has a header indicating it's total length. The AS controller will not attempt to read past the end of the first SOF. I would guess there is something else you are doing wrong which stops you from opening the EPCS device from Nios.
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