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Altera_Forum
Honored Contributor
10 years agoArrow Cyclone V SoCKit Hard DDR3 Memory controller interface
Hello all, I have a query with respect to the implementation of the Hard Memory controller + UniPHY interface for the Cyclone V SoCKIT development board (https://www.arrow.com/en/products/so......
Altera_Forum
Honored Contributor
10 years agoHello Thiago,
Thank you. it works. But, do you have any idea why the design runs only at 300 MHz?