ARM DS 5 script to initialize and load code in SDRAM

Dear ixpress,

I think this is not in the "bootloading" topic.

On Cyc V SoC DB, both the HPS-side memory controller , and FPGA-side memory controller has 1-1 GBs of DDR3 memory capacity.

-If HPS side SDRAM is used I suggest to examine altera applications (after a properly installed Quartus + DS5 AE):

<installed_altera_dir>\embedded\examples\software

-If FPGA-side SRAM is used, I suggest to examine built-in template applications in NiosII_EDS.

See memory_test template example.

Formerly, I have successfully tried this above memory test template on baremetal level (ARM) with replacing of some SOCAL/HWLIB functions.

See: <installed_altera_dir>\embedded\ip\altera\hps\altera_hps\doc\ (two different index.htmls)

Best regards,

Zsolt