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originally posted by samlittle@May 5 2006, 11:24 PM
hi hippo,
thanks for your answer. i use ocidec because altera only guarantees altcf core that support pio mode 0. so, i want to make my design more flexible. in your reply, you say only need to modify ptf how can i do it? moreover, i ever monitored altcf timing in signaltap ii at 50mhz of nios2 system clk, its result only meet pio mode 0 timing(600nsec). so, it maybe don't reach more higher mode unless i maybe increase system clk.
regards,
sam
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SLAVE ide
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Alignment = "native";
Address_Width = "4";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "530ns";
Write_Wait_States = "500ns";
Setup_Time = "70ns";
Hold_Time = "30ns";
Edit these wait timing in your ptf, then regenerate in sopc builder.