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Altera_Forum
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21 years ago

Any example Master Ports available?

Hello, Altera or anyone else have an example demonstrating external master logic driving an SOPC system? I've got one "working" but only if I set a very low fmax. The particulars ar...
Altera_Forum's avatar
Altera_Forum
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21 years ago

Hi Mike,

Thank for your help.

I tried the incrementing the address as you say and tying the bottom two bits low. No change. (this was one of the first things I tried weeks ago)

I probably wasn't clear on WEn. It's not registered with wait_request, but the CPUCLK. WEn is dependent on wait_request though since WEn cannot deassert until the next rising edge where wait_request is not asserted. (We've also tried the interpretation that WEn asserts as long as necessary for wait_request to assert and to deassert before WEn deasserts.)

Here is a puzzling timing violation. It complains about negative slack FROM lpm_counter|...|lpm_counter_stratix:wysi_counter|pre_hazard[0]~28 TO sdram:the_sdram|sdram_input_efifo_module|entry_1[1] From Clock alt_pll|clk0 To alt_pll|clk0.

Very confusing since there is at least two latches inbetween the output of this counter and the input to the SOPC system and thus on to sdram.

I can't imagine that anyone cares about whats on the other side of a latch that is registered to the CPUCLK. (?) Shouldn't anyone reading the latches output simply get what's there at the time of the read?

This don't care attitude seems to be what I'm working with for any external-to-the-cyclone peripheral. I simply present the proper signals in proper sequence and everyone is happy. On this internal-to-the-Cyclone peripheral however there is something more obscure going on.

I recently registered all in and out signals from the Master Port right at the Master Port in an attempt to compartmentalize the operations, but as you see in the warnings the build process is making obscure connections. And I don't doubt the warnings indicate real problems because lowering fmax to what it says is legal results in proper operation. (ie system doesn't lock up)

It's not a system overload issue, because I can generate all of this data (test data) within one of my Nios CPUs and no problems whatsoever.

If I had any pins left I'd connect the two modules through an external path, but I don't. There must be some fpga 101 rule that we're violating?

Kerri,

Any feedback from the SOPC engineers?

Thanks,

Ken