Honored Contributor
Honored Contributor--- quote start ---
the timing analyzer does complain, but i'm not sure what do do about it.[/b]
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what are its specific complaints?
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originally posted by kenland@jul 14 2004, 06:41 pm
for example the only logic connected to the address port is an lpm_counter that gets loaded with the sdram buffer address and then increments 4 times for each 32 bit word.
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umm... four times? why not just increment by four? drive address[n-1:2] from the counter and drive address[1:0] with 0?
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originally posted by kenland@jul 14 2004, 06:41 pm
write_n is registered on cpuclk and either waits until wait_request is not active on a following rising clock.
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you're supposed to keep write_n driven, not gate it with waitrequest. the write cycle starts when you want it to; this isn't like a shared bus where you have to wait for the other guy to get off of it. (well, actually, you do, but you wait by asserting write_n and waiting for waitrequest to go low. there's no separate wait-for-bus-release step.)
<!--quotebegin-kenland@Jul 14 2004, 06:41 PM do you think it can be the timing violations even though the la looks fine? --- Quote End --- It could be. Could you post just the ADC-to-Avalon master interface code?
