Honored Contributor
Honored Contributor--- quote start ---
the data is coming from an adc at one 32 bit word every 570ns. the max it would ever be is 2mhz.[/b]
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so this adc's clock is much slower than the system clock and the data rate is pretty constant. transactions will look like a 32-bit write to ram every now and then, so you don't really need the dma avalon signals. i'll assume that you're properly synchronizing the adc signals to the avalon clock before proceeding. at that speed, all you really have to do is write a small state machine to grab a sample, then put it on the avalon bus, no pipelining needed.
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Originally posted by KenLand[/i]@ since it works at a lower fmax and we're not really burdening the system that much i'm kinda lost. --- Quote End --- That just sounds like a cycle/clock timing problem to me, as in jumping clock domains, not exceeding fmax. <!--QuoteBegin-KenLand[/i] i kinda suspect that the build process optimizes the conection between our external logic and the avalon/sdram to the extent that they are too intermingled. we don't have any of this problem with logic that is actually outside the cyclone chip. (where logical interfaces *must* be adhered to) --- Quote End --- Put your logic in a LogicLock region, variable size, and optionally put the SOPC module in another one. That should keep them apart. BTW, how are you dealing with waitrequest from the Avalon?
