Altera TSE driver and example program for lwIP (1.3.2)

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actually i have my sgdma Tx and sgdma Rx mapped on a DDR ,

the same DDR where the CPU data an instruction is mapped.

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I'm almost positive that this can't work. Every example I've seen has SGDMA writing to onchip memory.

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Now imagine i want to use an onchip ram for sgdma tx and sgdmarx instead of DDR.

(but CPU still mapped to DDR)

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I would agree with this too. :-)

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I tried direclty but this is not working.

if you have any idea .

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Maybe it's not working for a non-SGDMA or memory reason. Compare to an example (e.g. the Altera NEEK development kit Ethernet code) and see if you're in the ballpark setting-wise.

Bill A.

Thanks BillA,

My problem was solved by using an equivalent SOPC as in Altera NEEK development kit Ethernet code.

thanks for the idea .

Laurent

Hi,

Just want to say that the example compiles under 12.1 with no effort.

Then a question, i am getting a code size of 180KB. I have not started tuning the code yet, but do any of you thinks it's possible to get down to 30-40Kb for a simple telnet server?

I need a small footprint to get it into internal mem. Would make our life much easier.

Apus

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Then a question, i am getting a code size of 180KB. I have not started tuning the code yet, but do any of you thinks it's possible to get down to 30-40Kb for a simple telnet server?

I need a small footprint to get it into internal mem. Would make our life much easier.

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My guess as a long-time user of lwIP (going back 10 years now) is that 30-40k will not likely be possible. TCP takes up a good bit of code. I could see 60k possibly. If you find out the smallest you can make it, please post back so others will know what is the smallest possible footprint.

Bill A.

Hi,

I have read through several threads on the subject but haven't been able to find the answer I am looking for. I would like to use lwIP with Altera TSE with no OS to receive TCP. I need to support about 10MB/s (80 Mb/s) shared between multiple TCP connections. There is very little other processing on the NIOS II/f. From reading it seems that if I do the following:

1) Run out of on chip memory.

2) Increase Processor clock speed as much as possible (Using Stratix IV)

3) Add TCP checksum offloading

4) possibly some other optimizations like endian conversion

then i should be able to reach that speed but I was wondering if anyone could give me a more firm answer of if this is feasible or not.

Thanks,

Arthur

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Hi,

I have read through several threads on the subject but haven't been able to find the answer I am looking for. I would like to use lwIP with Altera TSE with no OS to receive TCP. I need to support about 10MB/s (80 Mb/s) shared between multiple TCP connections. There is very little other processing on the NIOS II/f. From reading it seems that if I do the following:

1) Run out of on chip memory.

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I would run just select parts - inet_chksum, some of ethernetif, and maybe the oft-used pbuf functions. For a start, move nothing and see how it goes. It's so easy to move functions to on-chip memory there's no urgency to do that up front.

And use code and data cache. 4k each if you can.

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2) Increase Processor clock speed as much as possible (Using Stratix IV)

3) Add TCP checksum offloading

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This is the biggest thing you can do. If not in hardware, using assembly for the checksum is still good. And an optimized memcpy too! The built-in memcpy is OK but can be better. Oh, and the macro SMEMCPY replace with an inline copy - it's always a small copy with a constant size.

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4) possibly some other optimizations like endian conversion

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For Cyclone-III the endian opcodes are included for htonl/ntohl. There was none for hton/ntoh - we did our own but I don't know if it's really used enough to matter.

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then i should be able to reach that speed but I was wondering if anyone could give me a more firm answer of if this is feasible or not.

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Yes, it's feasible. Close but I see not much reason for it not to work.

Bill A

Hello fellow adventurers,

I am currently trying to port the FreeRTOS+lwIP environment onto the Stratix-V fpga eval board under the Quartus-II 13.0sp1 toolset. I've already ran into a number of issues, but so far managed to plow through most (tool name changes, some FreeRTOS/lwIP syntax changes after upgrading to latest, etc..).

I was wondering if anyone else has tried running FreeRTOS+lwIP on Stratix V eval board, and if so, how successful were you?

I am happy to provide feedback/share my findings (assuming we don't scrap this approach and go with Micrium+NicheStack... not my preferred choice).

Thanks for your help!

sjp

The following optimization can be applied to lwip_tse_mac.c:

In function tse_sgdmaRx_isr: Replace the init_tset_descriptor function call (spans 6 or 7 lines) just after label _dump: with the following:

IOWR_32DIRECT(&tse_ptr->desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST].write_addr, 0, (u32_t) ethernetif->lwip_rx_pbuf[ethernetif->lwipRxIndexIsr]->payload);

IOWR_8DIRECT(&tse_ptr->desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST].control, 0, ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK);

I don't claim credit for this - I see they did this in the NIOS 12.1 TSE driver and it makes a lot of sense.

Bill A

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You can use the one that the dev kit will use when running e.g. the Interniche examples. If it doesn't come with a MAC address, you will have to use a temporary one but be sure to stay behind a router or directly connected to a PC. I use a real test MAC address from our block of addresses that I know is not in use locally.

Bill

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ims,can you send your project to me ?I have the same problem with you.my email is [email protected],thanks!