--- Quote Start ---
PETRAK, PHY chips usually have some pins intended to drive status leds. It is convenient to use them as a workaround to reduce slow MDIO exchange. For example, 88E1119R asserts LED2 pin on connect and de-asserts on disconnect. If you wire this signal into FPGA you will be able to read link status by PIO with zero overhead.
--- Quote End ---
IMS, in fact that is *exactly* what we did - we use the same PHY and used that LED on an FPGA input pin. I did not experiment with making that an interrupt but I wanted to. Detecting loss of link was not a real-time problem for us.
The workaround I mentioned wasn't just for the PHY but also for general poor and inconsistent interrupt latency on the external interrupt. The MDIO made it so bad we had to use the LED. We latched the effective start of the external interrupt to hide the normal latency that is added since we need to do something exactly timed off the external interrupt without bobble. So in effect the ISR handling is in the middle of the window from external interrupt to when we need the hardware to do its thing. We can handle this skew as long as the interrupt to hardware processing is the same.
Bill A.
Honored Contributor
