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Altera_Forum
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15 years ago

Altera TSE driver and example program for lwIP (1.3.2)

After many many requests and complaints about lack of support and/or documentation for support of lwIP for the Altera TSE, I have developed a drop-in TSE driver and example program and made this avai...
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Altera_Forum
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13 years ago

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I assumed that this will cause something like this. Interrupts you are talking about are all interrupts in system ? During the read from PHY all interrupts will be delayed ?

For us this is not big issue, we don't have such realtime processing.

So for Altera devices there is no ("right") way to handle info about link state from PHY without this issues ? :(

Thanks

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PETRAK, PHY chips usually have some pins intended to drive status leds. It is convenient to use them as a workaround to reduce slow MDIO exchange. For example, 88E1119R asserts LED2 pin on connect and de-asserts on disconnect. If you wire this signal into FPGA you will be able to read link status by PIO with zero overhead.