Altera TSE driver and example program for lwIP (1.3.2)

Igor,

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How could I expect this in advance?

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I didn't mean to be condescending. I guess we have to remember that zero-copy means "use the given pointer to the payload". Even so, the unaligned pointer was not your issue here. That was handled by the driver (and now I see why it's good to not take it out even with there being a copy). What got you is the "me called" SGDMA bug. Aligned or not the 1-byte transfer was not going to work.

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Yes, for UDP alignment is under developer’s control. I also had to reinvent some kind of “zero-copy reliable UDP”. I use LWIP for retransmitting only – this makes life easier. Actually, if you cook UDP packets in hardware, you can retransmit a packet without LWIP intervention at all – just instruct one SGDMA to ship out exactly what had been delivered into memory by another SGDMA.

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If you NAK each packet, yes. And sending is faster. I have a multi-nak protocol which might have to go back in the buffer and resend one or more packets. I actually build and checksum the IP and UDP headers in a static position and only patch the checksum before sending the packet header and payload. This is because most of the header doesn't change. lwIP could incorporate this too because once connected to a PCB, much of the header and that checksum part is static.

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Would be better to turn into ASSERT. (For those who like building pbufs by hand, like me :) ).

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Sure, good idea.

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If you only need to insert 1-3 bytes at the _end_ of packet, you may try standard “On-Chip FIFO Memory Core” (or very simple custom component) and mux its output with the SGDMA (though I never implemented this in hardware). I don’t know readily available solution for general case (when incomplete words are inside the packet). Should not be very difficult to code. The main challenge seems to be repacking of the stream to become Avalon-ST complaint: e.g. <sop4><4><1><4><2eop> into <sop4><4><4><3eop>.

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Too bad there's no MAC register to "queue a byte into the frame buffer". In reality if it were designed well you should be able to use the MAC in either SGDMA mode or direct CPU write mode. It's just receiving data. You would need START, DATA, and STOP registers to start, send data, and terminate a packet.

Bill