Altera TSE driver and example program for lwIP (1.3.2)

The first thing would be to check the PHY chip pins, mostly the power supplies and the clock.

But there must be something wrong with your FPGA design, as you should at least get something on the MDIO line coming from the FPGA... Are you sure that the network driver is actually trying to talk to the PHY? Check how you connected the 3 MDIO signals from the TSE to the MDIO pin. You should have a bidirectional buffer, with the output enable at the correct polarity.