Altera TSE driver and example program for lwIP (1.3.2)

Igor -

I spoke to RF at Altera on Weds AM - he not only wrote SSS but also the offload example. We touched on several things, on this subject I can share the following.

RF's take on this was that both of the examples could/should be used in tandem by developing a protocol in which data bursts passing through the bypass would be preceded by a tcp/ip control packet specifying data type/destination queue, etc. allowing the nios to set up a transfer. A modification to the packet checker would be made to interface it with a fifo and back it with a stream-in/memory mapped output SGDMA engine that would hammer the memory into dram - the fifo acting like an elastic store to ensure refresh cycles, etc wouldn't drop data.

My take on the subject is slightly more cynical; Interniche has a product; by allowing people in the Altera community to use a performance-castrated version of it, they get small companies to design them into their embedded solution. When they find that the performance is limited, they buy the subscription version that includes performance enhancements like BillA made to the LwIP stack. Since the performance metrics are published for all to see, people know what they are getting into before the design in. If you don't find the metrics in the 40,000 pages of documentation Altera published, it is not their fault.

I had him on the phone for an hour - I can tell you this: At the end of the conversation I had decided that it would be far quicker and easier to pitch the Interniche stack and implement LWIP in my design than to implement the HW speed up advocated by RF - if I find that in my embedded system that the performance isn't there then I will take the HW route.

my best to all

-crayner