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Altera_Forum
Honored Contributor
16 years agoI've a custom opcode that uses the 'B' register number to select between:
- 32 bit byte reverse - 16 bit byte reverse - 32 bit bit reverse - 16 bit bit reverse - 8 bit bit reverse It should be possible to make the supported transformations configurable in the sopc builder - to save fpga real estate, but we aren't that short of gates. I also did G.711 a-law <=> u-law in combinatorial logic, but they take about 12ns :-(