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Altera_Forum
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10 years ago

Altera JTAG UART used by kernel does not match IRQ assignment made in Qsys

Hi all, I'm currently developing a 3.10.31-ltsi kernel that running on a Nios II-based system. This system also contains several components including an Altera JTAG UART, USB host controller a...
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Altera_Forum
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10 years ago

Hi Brad,

We tried to do some analysis on this here.

Instead of forcing IRQ number in altera_jtag_probe, we tried to notice effect of manual change in dts file. In that we observed following,

JTAG UART was assigned IRQ 1 when we set interrupts = <0> in DTS file for jtaguart.

JTAG UART was assigned IRQ 2 when we set interrupts = <1> in DTS file for jtaguart.

JTAG UART was assigned IRQ 2 when we set interrupts = <2> in DTS file for jtaguart.

We did above only to notice effect of interrupt number assigned in DTS to jtaguart and how it is actually selected during build. This is for system in which Timer is at IRQ 0, JTAG is at 1 and Host Controller is at 2. This is little bit different than yours. But in this, we are getting same problem.

Based on this, it seems (or say apparent ) it is making some mistake in interpreting interrupt number assigned to jtaguart during the time it parses DTS.If we can get location from where ( or how ) DTS information is get collected, we shall be able to get some breakthrough. This is just my thought. You might have better way for debugging.

Thanks,

Bhaumik