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Altera_Forum
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10 years ago

Altera_Avalon_SPI Cyclone II DSK

I have a NIOS II/s processor at 50 MHz that has an two SPI's which interfaces with TI's AIC23 on the Cyclone II DSK board. One (master) SPI programs the AIC23. Other (Slave) SPI does the data transfe...
Altera_Forum's avatar
Altera_Forum
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10 years ago

I believe the Altera_Avalon_SPI is "slave" mode has problems. If not, I want to see the code/QSYS for a simple system to read/write 10 msec of data at 44.1 KHz sample rate from the AIC23 on a Cyclone 2 DSK board.