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SDavi9's avatar
SDavi9
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Agilex™ 5 FPGA E development Kit NIOS Design

Is there a development kit design, preferably in VHDL, for the Agilex™ 5 FPGA E development Kit that implements a NIOS II Tx and Rx using the FMC connector and an external optical device ?
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  • tehjingy_Altera's avatar
    tehjingy_Altera
    1 year ago

    Hi


    Yes, the top levels are in VHDL.

    They are just simple connection for the Nios V Processor.


    Regards

    Jingyang, Teh


tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


Sorry that we do not have any VHDL only example design for interfacing with the Nios V TX and RX on FMC connector.


However we have a Hello World Example Design Application running on top of the HAL API.

This method will be the best method on interfacing with any IP using the Nios V.


Below link might help kick you off in the right direction

https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/24.3.1/niosv_g/niosv_g_helloworld/docs/Agilex%E2%84%A2_5_FPGA_Nios%C2%AEV_g_Processor_Helloworld_Design.pdf


Regards

Jingyang, Teh


SDavi9's avatar
SDavi9
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Dear Jingyang,

Thank you so much for getting back to me so quickly. I will check it out. Are the top levels in VHDL ?

Best regards

Shmuel