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Altera_Forum's avatar
Altera_Forum
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15 years ago

Adding ssram to NIOS

Hello!

I would like to add some RAM to the NIOS processor. I am using the NEEK kit.

So in SOPC builder, I have added ssram. As there was an error message, I also added

an AVALLON MM tristate bridge.

Apparently SOPC is happy with it, there are no errors. Just in case, I also looked to

the SOPC design of Cyclone III NIOS II video sample code. The ssram is connected

the same way, so I suppose this part is right.

sram clock problem

Now when I generate the system, I obtain the following instantiation sample: 

niossram niossram_inst
  (
    .address_to_the_ssram            (address_to_the_ssram),
    .adsc_n_to_the_ssram             (adsc_n_to_the_ssram),
    .bw_n_to_the_ssram               (bw_n_to_the_ssram),
    .bwe_n_to_the_ssram              (bwe_n_to_the_ssram),
    .chipenable1_n_to_the_ssram      (chipenable1_n_to_the_ssram),
    .data_to_and_from_the_ssram      (data_to_and_from_the_ssram),
    .out_port_from_the_LEDs          (out_port_from_the_LEDs),
    .outputenable_n_to_the_ssram     (outputenable_n_to_the_ssram),
    .reset_n                         (reset_n),
    .sysclk                          (sysclk)
  );

However, in this instantiation, there is no clock dedicated to SRAM.

So here is the problem: how do I get an output from NIOS to SRAM?

sram address bus problem

I have been looking at samples, namely the NEEK_VIP_DEMO_LCD_SVGA, just

to know which pins go where. There I noticed that the addresses don't

begin at 0, but at 1. I was told that it's because the NIOS input is 8

bit and therefore the 2 last bits are unused. Shouldn't it begin at 2

in this case?

Now isn't there a problem if I conect

Now I have looked at the pinout of the cyclone_III_3c25_niosII_video and the

scram clock is at pin labeled "PIN_A2". So if I don't assign some clock

to this PIN_A2 in my pin assignment, I guess the scram will get no clock.

Can anyone tell me how to solve this?

sram data bus problem

Now I have tried to compile as is. But there is another problem: I get this message:

Error: Can't place multiple pins assigned to pin location PIN_D1 (IOPAD_X0_Y27_N7)

Error: Can't place multiple pins assigned to pin location PIN_H3 (IOPAD_X0_Y22_N7)

Pins D1 and H3 are the data bus D1 and D0.

But I verified in NEEK_VIP_DEMO_LCD_SVGA (this one compiles) that the data bus

is exactly at the same pins. Could anybody give me hints?

Thanks.

Pascal

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi,

    I found this thread on the search of how to put the ssram into operation. My ssram seems to work now, so I write how I think it is:

    --- Quote Start ---

    Shouldn't it begin at 2 in this case?

    --- Quote End ---

    You are right, for the ssram it should begin at 2, because it has a 32 bit word size. But in the example there is also the flash memory which has a word size of 16 bit, and both memorys share the same addressbus. So I guess for the sake of the flash it includes a[1].

    My sopc don´t use the flash so I left tristate-bridge at defaults. (no bus sharing, because senseless without more than one slave)

    My sopc has a 20 bit addressbus for the ssram. Makes sense because 2^20 = 1 M, so one address for each byte of the ssram-memory as mentioned in "Avalon Interface Specifications".

    I took bit 19 to 2 of this addressbus to the flash_sram_a[19..2] pins according to CIII FPGA Starter Board Reference Manual.

    At least a hello world programm runs in that way (I haven´t tested more than that till now). I hope the tristate bridge manages the writebyteenable bus bw_n to use the complete memory, but still have to test that.

    --- Quote Start ---

    Now I have looked at the pinout of the cyclone_III_3c25_niosII_video and the

    scram clock is at pin labeled "PIN_A2". So if I don't assign some clock

    to this PIN_A2 in my pin assignment, I guess the scram will get no clock.

    Can anyone tell me how to solve this?

    --- Quote End ---

    I think you just have to put a clock signal with apropriate frequency (same frequency as defined in sopc) on this pin.

    --- Quote Start ---

    sram data bus problem

    Now I have tried to compile as is. But there is another problem: I get this message:

    Error: Can't place multiple pins assigned to pin location PIN_D1 (IOPAD_X0_Y27_N7)

    Error: Can't place multiple pins assigned to pin location PIN_H3 (IOPAD_X0_Y22_N7)

    Pins D1 and H3 are the data bus D1 and D0.

    But I verified in NEEK_VIP_DEMO_LCD_SVGA (this one compiles) that the data bus

    is exactly at the same pins. Could anybody give me hints?

    --- Quote End ---

    Follow the advices in this thread:

    Damn, I can´t post links so use google and take the first hit. Google for:

    "problems with pin assignments with cyclone iii starter board"

    Regards

    Andreas
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hello Andreas!

    Thanks for your reply!

    Here is a report (http://passworld.co.jp/forummsp430/viewforum.php?f=18) of what I did. The first tutorial works fine, the second one

    will certainly work as soon as I can solve the SSRAM clock problem.

    --- Quote Start ---

    Hi,

    I think you just have to put a clock signal with apropriate frequency (same frequency as defined in sopc) on this pin.

    --- Quote End ---

    Yes, I know that, but my problem is simply: how do I do that?

    I know from many sources (schematics, other sample programs, etc) that the clock

    has to be wired to PIN_A9 (as far as I remember correctly) and that the SSRAM

    clock has to be wired to PIN_A2. When I added the NIOS processor in SOPC builder,

    the clock signal was automagically generated and could be found in the "*_inst.v" file.

    Now in pin planner, I have assigned the clock pin to A2 and it works (the first tutorial

    works).

    Now I canot assign the clock to A9. Not in pin planner anyway, because in this case

    SSRAM will have a clock, but NIOS will have no clock anymore.

    I suspect I have to create a new node (for instance ssram_clk), and use one of the

    tools to make a bridge from sysclk (input) to ssram_clk (output).

    So in short: how would you do that?

    --- Quote Start ---

    Follow the advices in this thread:

    Damn, I can´t post links so use google and take the first hit. Google for:

    "Problems with pin assignments with Cyclone III starter board"

    --- Quote End ---

    Yes, in the meantime, I found the solution, and there is an extensive

    explanation in my "Tutorial 2-1: NIOS + SRAM" in the link above.

    Thanks!

    Pascal