Add other file (vhdl) in project with .qip.

Just to understand your setup, I think you have a Qsys system, which you have generated, with some ports, ie clock and reset exported (within Qsys) and you have another VHDL file that you would like to connect it to the Qsys system and extra pins that you would want to assign to some pins?

If the above statement is true, you will need to create a top level RTL (or another VHDL file) to instantiate both the Qsys system and your own VHDL file and connect them. You will need to set the top level RTL as the top level entity. It should also contain all the pins that needed to be assigned at the pin planner.