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Altera_Forum
Honored Contributor
14 years agoMy clock configuration at the QSys is correct. The SDRAM clock is -67 degrees from my sys_clock and it is running at a supported speed (took a look at the datasheet)
I made this SDC file:create_clock -period 20.000 -name clkin_50
derive_pll_clocks
derive_clock_uncertainty