Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- Thanks Ted for your reply> but I have an address span of 32 byte or (16 byte for each input), here what is the base address of the output ? --- Quote End --- You would need to review the custom component (Verilog/VHDL) you created and understand what address is supplied to it in order to read the 'output'. It sounds like maybe you havent declared a wide enough address space to fit (3) 128-bit elements?