Altera_Forum
Honored Contributor
21 years agoAccessing FPGA RAM section
Dear all,
how is it possible to tell the linker to place variables in a RAM that is in the FPGA? I have the following problem: I got a design with 12k RAM on FPGA and in my software project there is a buffer that has to be placed in this RAM. So what I do is: UINT8 gc_buffer[8][1536] __attribute__ ((section ("int_ram"))); This places the variable into the RAM. Then the linker complains that: /cygdrive/c/altera/kits/nios2/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc-lib/nios2-elf/3.3.3/../../../../nios2-elf/bin/ld section int_ram [0000621d -> 00006818] overlaps section .text [00000328 -> 00018537] However in the linker file generated.lx in the syslib I can not find the segment overlap: MEMORY { reset : ORIGIN = 0x01000000, LENGTH = 32 ext_sdram_UNUSED : ORIGIN = 0x00000000, LENGTH = 32 ext_sdram : ORIGIN = 0x00000020, LENGTH = 16777184 ext_flash : ORIGIN = 0x01000020, LENGTH = 8388576 int_ram : ORIGIN = 0x01800000, LENGTH = 12288 } My question is does anybody have experience and got give me a top tip? Thanks nathan