Altera_Forum
Honored Contributor
15 years agoAccess-duration between reading 2 time from a perepherial
Hi Folks,
i implemented a RTC with an resolution of 8 ns with an memory-mapped avalon-interface for reading the timestamps. if i read from this device with nios II/f 2 times, the difference between them is 632-720 nanoseconds. The application is built on MicroC/OS II. They are running in 2 different Clock-Domains Timer(125 MHz), NIOS runs with 100 MHz. Domaincrossing without Clock-Crossing-Bridge, generated by Avalon-Interconnect-Fabrik. Main-Memory is DDR2-RAM in Halfdatarate 100 MHz, high performance cotroller 1. The Board is an Stratix II GX PCI Devikit. Cache 4 Kbyte, Data Cache 2 Kbyte.here is the sourcecode
//The Call
OS_ENTER_CRITICAL();
messure_avalon(PTPCORE_0_BASE);
OS_EXIT_CRITICAL();
-- THE Function
int messure_avalon(alt_u32 base){
TIME_STAMP* ts1 = (TIME_STAMP*) malloc(sizeof(TIME_STAMP));
TIME_STAMP* ts2 = (TIME_STAMP*) malloc(sizeof(TIME_STAMP));
ts1->seconds = IORD_PTPCORE_PRESENT_SECONDS(base);
ts1->nanoseconds = IORD_PTPCORE_PRESENT_NANOSECONDS(base);
//printf("hallo hallo");
ts2->seconds = IORD_PTPCORE_PRESENT_SECONDS(base);
ts2->nanoseconds = IORD_PTPCORE_PRESENT_NANOSECONDS(base);
printf("second-diff: %i\n", ts2->seconds - ts1->seconds);
printf("nanosecs-diff: %i\n", ts2->nanoseconds - ts1->nanoseconds);
free(ts1);
free(ts2);
return 0;
}
(Reading from Seconds, making an snapshot of nanoseconds.)
My question is the delay of 632-720 ns in the right range, how can i measure or estimate it ? Any suggestions. its round about 79-90 cycles, its a lot in my opinion. 40-45 cycles per read, and store to ddr2. Thank you so far best regards Mooresstudent